In the past few years, BGA semiconductor packages have enjoyed widespread use and success in the industry thanks to the many advantages they offer compared to the more traditional leadframe packages. The most obvious advantage they confer is their ability to host an increased number of interconnections within small dimensions whilst maintaining satisfactory ease of use and safety levels. This feature enables them to be used successfully in many high performance applications such as microprocessors, controllers, memories and chip sets, which require high density interconnection semiconductors.
With reference to FIG. 1, the basic architecture of a typical BGA package 1 is as follows: a solder ball base 17, providing external electrical interconnection with the rest of the system, underlies a substrate 2, usually made of an organic material, e.g., silicon, resin or glass, which in turn underlies a die 5.
The solder balls 20, which functionally replace the leads used in leadframe or Pin Grid Array (PGA) packages, are attached to a bottom 4 of the substrate 2 and their composition may include, for example, copper, tin, silver, lead, or bismuth. Typically, a 10×10 mm BGA package will contain up to 300 solder balls.
Solder balls are mechanically tougher than leads, thus enabling the device to better tolerate rough handling. Also, ball arrays allow for slightly imperfect placement during mounting as they are, to a certain extent, capable of self alignment to their attachment sites.
With reference now to FIG. 2, the substrate 2 is the key element of the package 1 and practically includes a small printed circuit board (PCB). As well as constituting the mechanical support of the silicon, the substrate 2 also has a fundamental role from the electrical point of view. Usually, a standard substrate is made of an organic core 13 covered by two copper foils 11, one on an upper surface 3 and one on a lower surface 4 of the substrate 2. By a dedicated mask etching process, these two copper foils create a connection between bond pads 14 situated on the upper surface 3, and ball pads 15 on the lower surface 4, and to which the solder balls 20 adhere. Plated through holes 12 (usually metal plated), also called vias, are drilled in the organic core 13 to provide electrical connections between the two copper foils. In order to do so, capture pads usually surround each via 12.
The upper surface 3 is surmounted by the die 5, which can be connected to the ball grid array either by wire-bonding 9 or flip-chip attachment, and which will typically require a large number of connections. Normally, the die 5 is attached to the substrate 2 (and/or to another die) with the aid of an adhesive material 16 that can be a glue or bi-adhesive tape.
With reference to FIGS. 3, 4 and 5 when more than one die 5, 6, 7, is required in a same package, it is quite common to stack them on top of one another. Stacked dice can either be of the same (or similar) size, in which case an “interposer” 10 is used between dice (as shown in FIG. 3) to allow a sufficient clearance (at least 250 μm, or example) for wire bonding, or can be of substantially different sizes, in which case they are piled up on top of each other in order of decreasing size, according to a pyramidal scheme, which takes the name of “pyramidal stack” (such as shown in FIGS. 4 and 5). This latter scheme, as opposed to the former “twin stack” scheme, does not require the use of an interposer.
The die, comprising a semiconductor device, is normally encapsulated with a protecting material (normally epoxy resin) 21 to confer protection from dust and other external agents including mechanical abuse.
Die stacking achieves the purpose of reducing the overall dimensions of the BGA package for a given number of required interconnections.
However, as the demand for further and improved miniaturization continuously increases, so does the interconnection density to be handled in a given BGA package. The challenge thus lies in being able to handle the required high (e.g., greater than 50) interconnection density with a minimum of footprint area (e.g., surface area at a base of the package).
Various approaches have been attempted in this respect, the most noteworthy being the ones briefly discussed below.
Application WO03061006, filed on Jan. 9, 2003 in the name of Micron Technology Inc, discloses semiconductor devices and stacked die assemblies and methods of manufacturing the devices and assemblies for increasing semiconductor device density. In one embodiment of the invention, it discloses a stacked die assembly comprising a first bottom die disposed on a substrate, a bonding element connecting bond pads on an active surface of the bottom die to terminal pads on the substrate, and a second die mounted on the bottom die. The second die has a bottom surface with a recessed edge along the perimeter of the die that provides an opening for the bonding element extending from the bond pads of the bottom die, thus eliminating the need for a spacer between the two dice for clearance. A second bonding element connects the bond pads on the active surface of the second die to terminal pads on the substrate.
Other BGA multi-chip packages are also known from U.S. Pat. No. 6,072,700 issued on Jun. 6, 2000 to Hyundai Electronics Industries Co., Ltd., U.S. Patent Application Publication No. US2004251529 published on Dec. 16, 2004 in the name of Lee and Lee, Japanese Patent Application No. 2004006990 published on Jan. 8, 2004 in the name of Nippon Electric Co., and U.S. Patent Application Publication No. 2003011062 published on Jan. 16, 2003 in the name of Watanabe.
However, the solutions devised in the prior art do not always achieve a full optimization of the space used, resulting in packages that are bulkier than desired. Also wire routing problems are quite common, especially when the smallest die requires a high density of interconnections, thus resulting in strong routing limitations or the need for unduly long wires, which in turn pose safety risks as they are susceptible to short circuiting. Also, long wires are detrimental to the electrical performance of the respective die especially in case of high working frequency.